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description the CXA1998BQ is an ic developed for analog signal processing in tape recorders. processing for both the recording and playback systems is achieved on one chip. features 11-bit serial data interface recording/playback mute function recording equalizer gp and fp can be adjusted externally. agc (automatic gain control) comparator for ams (automatic music sensor) recording/playback equalizer amplifier with 1.7 times speed switching absolute maximum ratings (ta = 25?) supply voltage v cc , v dd 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 645 mw operating conditions supply voltage v cc 6.5 to 10.0 v v dd 4.5 to 5.5 v structure bipolar silicon monolithic ic applications all analog signal processing in the cassette decks of tape recorders and compact music centers applicable head applicable to mitsumi electric co., ltd. playback head: bp-7442-cp-6973 recording/playback head: bc-9242-cb-9267 ?1 CXA1998BQ e98z31-ps recording/playback equalizer amplifier sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic)
? 2 CXA1998BQ block diagram and pin configuration (top view) d 1 d 2 d 3 d 4 d 5 d 6 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 m u t e a g c g a i n 1 9 . 5 d b 1 0 k 4 0 k r e c e q a m s g n d g n d g n d v d d v d d 2 0 k 2 0 k 2 0 k 2 0 k d 1 1 d 9 d 1 0 d 8 g n d d 7 g n d d 1 1 g n d d 9 g n d g n d g n d g n d g n d g n d v d d g n d 4 0 k a g c g a i n 1 9 . 5 d b 1 0 k r e c e q i r e f 3 6 3 5 3 4 3 3 g n d r f s 2 . 8 v 2 1 0 k g n d g n d 2 1 0 k g n d 2 1 0 k 2 1 0 k g n d 2 . 8 v a g c a g c o f f a e q b e q p b e q c t l r e c e q c t l d e c k a / b s p e e d s h i f t r e g i s t e r s l a t c h e s g p c a l a e q b e q a g c t c a g c i n 1 r e c i n 1 a g c o u t 1 r e c o u t 1 a m s g a i n a m s g n d a m s t c a m s o u t p b m u t e r m u t e i r m u t e s p e e d b p a b p b p l 1 p l 2 m 1 m 2 v d d l a t c h r f c v c c v g g n d a g c i n 2 r e c i n 2 a g c o u t 2 r e c o u t 2 d g n d x r e s e t d a t a c l k f p c a l p b o u t 1 p b f b 2 1 p b f b 1 1 p b i n b 1 p b i n a 1 p b i n a 2 p b i n b 2 p b f b 1 2 p b f b 2 2 p b o u t 2 i r e f
? 3 CXA1998BQ pin description pin no. 1 symbol dc voltage i/o equivalent circuit description gp cal 1.2v connects a resistor for determining the high-band peak gain of recording equalizer. reference setting resistance is 27k . i/o resistance 2 a eq i deck a equalizer switch. low: 120 s eq high: 70 s eq 3 b eq 2.5v (open ) i deck b equalizer switch. low: normal tape, 120 s eq medium: cro 2 tape, 70 s eq high: metal tape, 70 s eq 53k 4 agc tc 0.0v connects a resistor and capacitor for determining agc attack/recovery time constants. 1 v c c v c c g n d g n d 1 4 7 2 3 0 k v c c 1 4 7 g n d g n d v c c 2 v c c 1 4 7 5 0 k v c c g n d g n d 5 k 5 k 3 v c c g n d g n d v c c 2 2 0 0 1 0 0 k 5 0 0 5 0 0 2 1 4 7 2 4 2 0 0 5 k 4 (ta = 25 c, v cc = 8v, v dd = 5v, no signal, reset on)
? 4 CXA1998BQ 5 32 agc in1 agc in2 4.0v i agc signal input. input resistance changes between 50k and 100k . agc functions when the signal of ?0dbm or more is input to agc for agc on. (external 47 f//300k for pin 4) 50k 6 31 rec in1 rec in2 4.0v i recording equalizer input. 50k 7 30 agc out1 agc out2 4.0v o agc output. 147 8 29 rec out1 rec out2 4.0v o recording equalizer output. 147 v c c 1 4 7 4 0 k 5 0 0 1 0 v c c g n d g n d 3 5 0 0 2 5 p 8 2 9 v c c 1 4 7 1 8 7 5 2 5 0 0 4 v c c g n d v g s g n d 2 5 0 0 7 3 0 1 0 7 4 2 3 9 9 4 5 v g s v c c 1 4 7 5 0 k v c c g n d v g s 2 3 1 8 6 1 7 5 9 v g s g n d 6 3 1 v c c 1 4 7 1 0 k 4 0 k 4 v c c g n d v g s 5 3 2 pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
? 5 CXA1998BQ ams block ground. 9 ams gain 3.5v connects a resistor for determining ams signal detection level and a capacitor for determining hpf cut- off frequency. 10 ams gnd 0.0v 12 ams out 8.0v o ams output. no signal detection: high signal detection: low 11 ams tc 8.0v connects time constant for ams detection. v c c 1 4 7 g n d v c c g n d 1 0 0 k 1 0 9 1 1 v c c g n d 1 k g n d 1 4 7 v c c v c c g n d v c c 1 2 v c c v c c 1 0 k g n d 1 0 g n d pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
? 6 CXA1998BQ 13 pbmute 14 rmute1 5.0v connects a capacitor for setting time constant for playback mute on/off switching. 15 rmute output for recording mute on/off switch control signal. outputs d11 from pin 26 (data). 16 speed 5.0v o output for recording/playback equalizer speed switch control signal. outputs d9 from pin 26 (data). low: normal speed high: high speed (1.7 times) 17 bpa 5.0v o outputs d6 from pin 26 (data). 18 bpb outputs d5 from pin 26 (data). 19 pl1 outputs d4 from pin 26 (data). 20 pl2 outputs d3 from pin 26 (data). 21 m1 outputs d2 from pin 26 (data). 22 m2 outputs d1 from pin 26 (data). 23 v dd power supply of serial data interface block. 5.0v 1 3 1 4 v d d v d d 2 0 k 2 0 k g n d 4 1 4 7 g n d g n d connects a capacitor for setting time constant for recording mute on/off switching. 4 v d d 5 k g n d g n d v d d 4 5 k 2 0 k 1 5 1 6 4 v d d g n d g n d v d d 4 1 0 k 2 0 k 1 7 1 8 1 9 2 0 2 1 2 2 v d d 2 3 pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
? 7 CXA1998BQ 24 latch 27 xreset i serial data interface latch input. 25 data i serial data interface reset input. low: reset. at this time serial data outputs (pins 15 to 22) are all open (high). 26 serial data interface clock input. serial data interface serial data input. 28 dgnd 0.0v serial data interface block ground. clk 2 k g n d v d d 1 0 . 5 k 2 5 a g n d 3 0 k 5 p 4 3 0 k 2 4 2 7 4 k g n d v d d 1 0 . 5 k 2 5 a g n d 3 0 k 4 3 0 k 2 5 2 6 g n d 2 8 33 gnd 0.0v ground. 35 v cc 8.0v power supply. 34 vg 4.0v signal reference voltage. connects a capacitor for ripple rejection. 60k g n d 3 3 3 4 v c c 1 4 7 4 5 k 3 0 k 4 v c c g n d g n d 5 0 0 5 0 0 2 3 0 k 2 t o e a c h v g s 3 5 v c c pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
? 8 CXA1998BQ connects a resistor (12k ) for determining equalizer gains. 36 rfc 8.0v connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. 37 iref 38 47 pb out2 pb out1 2.8v o playback equalizer output. 147 48 fp cal 1.2v connects a resistor for determining the high- band peak frequency of recording equalizer. reference setting resistance is 27k . 3 6 v c c 1 4 7 v c c g n d 3 2 5 0 3 t o e a c h r f s v c c g n d 2 g n d 3 7 4 8 1 4 7 5 p v c c v c c g n d v c c 3 5 0 0 1 4 7 6 g n d 1 5 p 4 7 3 8 5 0 0 39 46 pb fb22 pb fb21 2.8v connects a capacitor for determining playback equalizer time constants, such as 120 s and 70 s. 3 9 4 6 v c c 1 4 7 3 g n d 2 k 2 k g n d g n d 4 7 k 3 4 r f s pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
? 9 CXA1998BQ 40 45 pb fb12 pb fb11 1.4v playback equalizer negative feedback. 105k 41 42 43 44 pb inb2 pb ina2 pb ina1 pb inb1 0.0v i playback equalizer input. 70k 4 1 4 2 4 3 4 4 4 5 7 0 k 1 0 p v c c g n d v c c g n d 6 v c c 4 0 g n d 1 k 1 k 2 1 0 k 2 1 0 k v c c r f s 2 1 0 k 5 k 6 1 4 7 3 0 p 1 4 7 note) ams gnd (pin 10), dgnd (pin 28) and gnd (pin 33) are each independent in the ic and are not connected. be sure tp ground each of the ground pins listed above. the resistance of open collector outputs (pins 15 to 22) can be connected vcc. pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
? 10 CXA1998BQ electrical characteristics (ta = 25 c, v cc = 8.0v, v dd = 5.0v, refer to electrical characteristics measurement circuit) item operating voltage current consumption measurement conditions min. typ. max. unit v cc v dd sum of v cc and v dd pin currents norm ?ns, no signal pin 4 external r300k //c47 f f = 1khz, vin = ?5dbm pin 4 external r300k //c47 f f = 1khz, vin = ?5dbm pin 4 external r300k //c47 f f = 1khz, vin = 0dbm pin 4 external r300k //c 47 f f = 1khz, vin = ?5dbm pin 9 external r9.1k , c0.015 f pin 11 external r100k //c0.1 f f = 5khz, 0db = ?1dbm (at pbeq reference output level) f = 315hz, vin = ?0dbm reference for frequency response f = 2.7khz, vin = ?8.5dbm at 120 s ?ns, 315hz f = 4.5khz, vin = ?3.8dbm at 120 s ?ns, 315hz f = 5.3khz, vin = ?2.5dbm at 120 s ?ns, 315hz f = 9.1khz, vin = ?7.8dbm at 120 s ?ns, 315hz 120 s ?ns, r l = 2.7k f = 1khz, thd + n = 1% 120 s ?ns, r l = 2.7k f = 1khz, vin = ?6.0dbm 120 s ?ns, rg = 470 ??weighting filter 120 s ?ns, rg = 470 , playback mute off 120 s ?ns, f = 1khz, vin = ?1.0dbm agc on output level agc on channel balance agc on distortion agc off output level no signal detection threshold level 120 s ?ns frequency response 120 s ?ns frequency response 70 s ?ns frequency response 120 s ?hs frequency response 70 s ?hs frequency response signal handling total harmonic distortion s/n ratio output offset voltage playback mute characteristics 6.5 4.5 13.5 ?3.0 ?.0 ?.5 ?1.5 ?3.0 ?.6 ?.2 1.8 2.1 ?0.0 55.0 2.4 8.0 5.0 19.7 ?1.0 0.0 0.3 ?.5 ?.2 ?1.0 0.8 0.6 3.0 3.6 ?.0 0.3 62.0 2.7 ?00 10.0 5.5 25.0 ?.0 2.0 1.5 ?.5 ?9.0 2.4 1.8 4.8 5.1 0.7 3.2 ?0 v v ma dbm db % dbm db dbm db dbm % db v db agc ams playback equalizer amplifier block
? 11 CXA1998BQ reference input level reference output level channel balance norm ?ns frequency response norm ?ns frequency response norm ?ns frequency response cro 2 ?ns frequency response cro 2 ?ns frequency response cro 2 ?ns frequency response metal ?ns frequency response metal ?ns frequency response metal ?ns frequency response norm ?hs frequency response norm ?hs frequency response norm ?hs frequency response cro 2 ?hs frequency response cro 2 ?hs frequency response cro 2 ?hs frequency response metal ?hs frequency response metal ?hs frequency response metal ?hs frequency response db norm ?ns, 315hz, input level at which reference output can be obtained norm ?ns, 315hz norm ?ns, 315hz, output level difference 1ch-2ch for ?7.7dbm input f = 3khz at norm ?ns, 315hz, reference output ?0db f = 8khz at norm ?ns, 315hz, reference output ?0db f = 12khz at norm ?ns, 315hz, reference output ?0db f = 3khz at norm ?ns, 315hz, reference output ?0db f = 8khz at norm ?ns, 315hz, reference output ?0db f = 12khz at norm ?ns, 315hz, reference output ?0db f = 3khz at norm ?ns, 315hz, reference output ?0db f = 8khz at norm ?ns, 315hz, reference output ?0db f = 12khz at norm ?ns, 315hz, reference output ?0db f = 5khz at norm ?ns, 315hz, reference output ?0db f = 15khz at norm ?ns, 315hz, reference output ?0db f = 20khz at norm ?ns, 315hz, reference output ?0db f = 5khz at norm ?ns, 315hz, reference output ?0db f = 15khz at norm ?ns, 315hz, reference output ?0db f = 20khz at norm ?ns, 315hz, reference output ?0db f = 5khz at norm ?ns, 315hz, reference output ?0db f = 15khz at norm ?ns, 315hz, reference output ?0db f = 20khz at norm ?ns, 315hz, reference output ?0db ?7.7 ?0.0 0.0 ?.7 3.5 10.2 3.2 9.0 15.8 4.0 8.1 12.8 ?.8 8.7 13.9 5.4 15.2 18.7 7.0 14.5 18.4 ?9.2 ?.5 ?.9 2.1 7.6 1.9 7.1 12.5 2.8 6.7 10.9 ?.6 6.6 10.9 4.2 13.1 15.7 5.8 12.7 15.9 ?6.2 1.5 ?.5 5.7 14.6 4.3 11.1 21.0 5.2 9.7 15.9 1.2 10.8 16.4 6.6 17.3 21.7 8.2 16.3 20.9 dbm recording equalizer amplifier block item measurement conditions min. typ. max. unit
? 12 CXA1998BQ norm ?ns, r l = 2.7k f = 1khz, thd + n = 1% norm ?ns, r l = 2.7k f = 1khz, 0db norm ?ns, rg = 5.1k ??weighting filter norm ?ns norm ?ns, f = 1khz 8db a-eq (pin 2) a-eq (pin 2) b-eq (pin 3) b-eq (pin 3) b-eq (pin 3) signal handling total harmonic distortion s/n ratio output offset voltage recording mute characteristics 8.0 57.0 3.6 0.0 2.5 0.0 2.2 4.2 8.8 0.2 60.6 4.0 ?00 0.5 4.4 ?0 0.5 v cc 0.5 2.8 v cc db % db v control voltage low level 1 control voltage high level 1 control voltage low level 2 control voltage medium level 1 control voltage high level 2 note) norm ?ns: normal tape ?normal speed norm ?hs: normal tape ?high speed cro 2 ?ns: cro 2 tape ?normal speed cro 2 ?hs: cro 2 tape ?high speed metal ?ns: metal tape ?normal speed metal ?hs: metal tape ?high speed 120 s ?ns: eq = 120 s ?normal speed 120 s ?hs: eq = 120 s ?high speed 70 s ?ns: eq = 70 s ?normal speed 70 s ?hs: eq = 70 s ?high speed db v recording equalizer amplifier block item measurement conditions min. typ. max. unit
? 13 CXA1998BQ v il (latch/clk/data/xreset) (pins 24, 25, 26, 27) v ih (latch/clk/data/xreset) (pins 24, 25, 26, 27) v ol , i ol = 2ma (max) (pins 15, 16, 17, 18, 19, 20, 21, 22) i oz leak current which flows to the output pin when i oz output is open; applied voltage is 10v. (pins 15 to 22) (1) f ck (2) t wc (3) t wr (4) t sdk (data ? clk) (5) t hcd (clk ? data) (6) t wd (7) t sld (latch ? data) (8) t hcl (clk ? latch) (9) t hlc (latch ? clk) low level input voltage high level input voltage low level output voltage high level output off leak current maximum clock frequency minimum clock pulse width minimum reset pulse width minimum data setup time minimum data hold time minimum data pulse width minimum latch setup time minimum latch hold time minimum clock hold time 0.0 3.5 0.0 500 1.5 v dd 0.5 1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 note) v dd is cpu supply voltage of 5.0v. v cc is 10.0v for high level output off-leak current. the threshold levels of low level input voltage and high level input voltage depend on v dd . input level detection is done by comparison with v dd /2. (refer to equivalent circuit?of pin description.) s v a khz item measurement conditions min. typ. max. unit 11-bit serial data interface block
? 14 CXA1998BQ timing chart for 11-bit serial data interface (v dd = 5.0v) t w c t w c t w d t h c d t s d k 1 . 5 v 3 . 5 v d 1 d 2 1 . 5 v 3 . 5 v 1 . 5 v t s l d 3 . 5 v 1 . 5 v 3 . 5 v 1 . 5 v t h c l d 1 0 d 1 1 t h l c t w r c l k d a t a l a t c h c l k d a t a l a t c h x r e s e t
? 15 CXA1998BQ electrical characteristics measurement circuit 6 7 8 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 7 3 9 4 6 4 7 4 8 3 6 3 5 3 4 g p c a l a e q b e q a g c t c a g c i n 1 r e c i n 1 a g c o u t 1 r e c o u t 1 a m s g a i n a m s g n d a m s t c a m s o u t p b m u t e r m u t e i r m u t e s p e e d b p a b p b p l 1 p l 2 m 1 m 2 v d d l a t c h r f c v c c v g g n d a g c i n 2 r e c i n 2 a g c o u t 2 r e c o u t 2 d g n d x r e s e t d a t a c l k f p c a l p b o u t 1 p b f b 2 1 p b f b 1 1 p b i n b 1 p b i n a 1 p b i n a 2 p b i n b 2 p b f b 1 2 p b f b 2 2 p b o u t 2 i r e f r 1 1 4 1 0 k r 1 0 3 2 . 2 k s 3 6 a s 3 6 b r 1 1 3 1 0 k r 1 0 2 2 . 2 k s 3 5 a s 3 5 b r 1 1 2 1 0 k r 1 0 1 2 . 2 k s 3 4 a s 3 4 b r 1 1 1 r 1 0 0 2 . 2 k s 3 3 b r 1 1 0 r 9 9 2 . 2 k s 3 2 b r 1 0 9 r 9 8 2 . 2 k s 3 1 b 1 0 k s 3 3 a 1 0 k s 3 2 a 1 0 k s 3 1 a r 1 0 8 r 9 7 2 . 2 k s 3 0 b 1 0 k s 3 0 a r 1 0 7 r 9 6 2 . 2 k s 2 9 b 1 0 k s 2 9 a r 1 0 6 c 3 4 0 . 1 s 5 7 a 1 0 k s 5 3 r 1 0 5 s 5 7 b 1 0 k s 5 4 c 3 3 0 . 1 s 5 6 b s 5 6 a s 5 8 h s 5 8 g s 5 8 f s 5 8 e s 5 8 d s 5 8 c s 5 8 b s 5 8 a 2 3 5 v 5 v l a t c h 2 . 2 / 2 5 v c 3 0 2 . 7 k r 8 6 s 1 2 d 4 . 7 / 2 5 v c 2 8 1 0 k r 7 9 0 . 4 7 / 5 0 v c 2 6 0 . 4 7 / 5 0 v c 2 2 1 0 k r 8 9 s 2 7 b 1 0 0 r 8 4 s 2 7 a 1 0 0 r 8 1 s 2 1 b r 7 6 3 9 0 k r 7 2 4 7 k s 2 1 a 5 . 1 k 3 2 3 3 1 0 k r 6 1 4 7 / 2 5 v c 1 8 8 v 4 7 / 2 5 v c 1 7 4 7 / 2 5 v c 1 5 1 k r 5 b s 1 5 c l k d a t a x r e s e t 3 8 4 0 1 0 0 r 4 4 4 7 / 2 5 v c 1 0 4 . 7 k r 3 7 4 7 0 r 5 0 4 1 0 . 0 1 8 c 1 4 1 c 9 4 . 7 / 2 5 v c 4 8 2 k r 3 5 4 7 0 r 4 9 1 c 8 4 . 7 / 2 5 v c 3 8 2 k r 3 4 4 7 0 r 4 8 1 c 7 4 . 7 / 2 5 v c 2 8 2 k r 3 3 4 7 0 r 4 7 1 c 6 4 . 7 / 2 5 v c 1 8 2 k r 3 2 4 2 4 3 4 4 1 0 0 r 4 3 4 7 / 2 5 v c 5 4 . 7 k r 3 6 0 . 0 1 8 c 1 3 4 5 2 . 2 / 2 5 v c 1 1 2 . 7 k r 3 8 s 1 2 b 2 7 k r 4 2 2 . 2 / 2 5 v 2 . 7 k s 1 2 a 1 2 k r 4 5 1 0 0 r 4 1 s 1 1 a 1 0 k r 5 2 s 1 1 b 2 . 2 / 2 5 v c 2 9 2 . 7 k r 8 5 s 1 2 c 1 0 k r 8 8 s 2 6 b 1 0 0 r 8 3 s 2 6 a 4 . 7 / 2 5 v c 2 7 1 0 k r 7 8 s 2 2 b 0 . 4 7 / 2 5 v c 2 5 r 7 4 s 2 5 b r 7 3 3 9 0 k r 7 1 4 7 k r 8 0 1 0 0 0 . 4 7 / 5 0 v c 2 1 5 . 1 k s 2 2 a 5 . 1 k r 6 8 3 0 0 k r 6 6 4 5 4 7 / 2 5 v c 2 0 3 s 2 0 s 1 9 s 1 8 m e t a l c r o 2 n o r m 1 0 k r 6 3 1 0 k r 5 9 2 4 . 2 v 2 . 5 v 0 . 5 v 2 7 k r 5 6 1 9 . 1 k r 9 0 0 . 0 1 5 c 3 1 9 1 0 0 . 1 c 3 2 1 0 0 k r 9 2 1 0 0 k r 9 3 1 0 k r 9 4 s 2 8 g n d d c o u t p u t t l 0 7 2 + 6 0 0 r 3 0 a t t s 5 b s 5 a 6 d b a t t s 4 b s 4 a 9 d b a t t s 3 b s 3 a 1 7 d b a t t s 2 b s 2 a 2 9 d b a t t s 1 b s 1 a 4 0 d b a c i n p u t c h a r g e 1 c h a r g e 2 1 0 k r 5 1 1 0 0 r 4 0 s 1 0 b s 1 0 a 1 k h z b a n d p a s s f i l t e r ( 2 0 d b ) a u d i o ( 2 2 . 2 h z 2 2 . 2 k h z ) f i l t e r " a " w e i g h t i n g f i l t e r 3 0 d b a m p b u f s 5 0 5 s 5 0 4 s 5 0 3 s 5 0 2 s 5 0 1 a c o u t p u t 1 0 0 k r 5 3 6 g n d 4 . 7 k r 5 4 1 0 k r 6 4 s 1 6 5 . 1 k r 6 9 c 2 4 0 . 1 s 2 5 a r 7 5 c 2 3 0 . 1 s 1 4 r 3 9 c 1 2 0 . 1 c 1 6 1 2 0 s 7 0 s s 9 s 8 s 7 s 6 s 1 3 s 5 5 s 2 3 0 . 1 c 1 9 b e q a e q s 1 7 s 3 7 s 2 4
? 16 CXA1998BQ application circuit g p c a l a e q b e q a g c t c a g c i n 1 r e c i n 1 a g c o u t 1 r e c o u t 1 a m s g a i n a m s g n d a m s t c a m s o u t p b m u t e r m u t e i r m u t e s p e e d b p a b p b p l 1 p l 2 m 1 m 2 v d d l a t c h r f c v c c v g g n d a g c i n 2 r e c i n 2 a g c o u t 2 r e c o u t 2 d g n d x r e s e t d a t a c l k f p c a l p b o u t 1 p b f b 2 1 p b f b 1 1 p b i n b 1 p b i n a 1 p b i n a 2 p b i n b 2 p b f b 1 2 p b f b 2 2 p b o u t 2 i r e f v d d 1 0 0 k v d d v d d 4 7 k v d d 4 7 k v d d 4 7 k v d d 4 7 k v d d 4 7 k v d d 4 7 k v d d 4 7 k v d d 4 7 k g n d 0 . 1 g n d 2 2 1 0 0 k 1 0 0 k 0 . 1 2 . 2 k 0 . 1 g n d 2 7 k v c c 3 . 3 m e g 4 7 0 . 4 7 0 . 1 2 . 7 k 4 . 7 1 0 k 2 . 2 2 . 2 1 0 k g n d g n d g n d g n d v c c v c c g n d 2 7 k 4 7 1 0 0 g n d 0 . 0 1 8 4 7 1 0 0 g n d 0 . 0 1 8 2 . 2 1 0 k g n d g n d 1 2 k 1 0 0 k g n d 1 0 0 k g n d 1 0 0 k g n d v d d 2 . 2 g n d 2 . 2 g n d 0 . 1 2 . 7 k 4 . 7 1 0 k 0 . 4 7 g n d g n d 4 7 g n d 4 7 g n d 1 0 0 1 k v c c b i a s o s c g n d d e c k - a p b - h e a d g n d g n d r / p - h e a d d e c k - b g n d 1 5 0 p 8 2 0 p 1 0 k 1 8 0 p 1 2 m h g n d 1 5 0 p 1 8 0 p 1 2 m h 8 2 0 p 1 0 k d 1 d 2 d 3 d 4 d 5 d 6 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 m u t e a g c g a i n 1 9 . 5 d b 1 0 k 4 0 k r e c e q a m s g n d g n d g n d v d d v d d 2 0 k 2 0 k 2 0 k 2 0 k d 1 1 d 9 d 1 0 d 8 g n d d 7 g n d d 1 1 g n d d 9 g n d g n d g n d g n d g n d g n d v d d g n d 4 0 k a g c g a i n 1 9 . 5 d b 1 0 k r e c e q i r e f 3 6 3 5 3 4 3 3 g n d r f s 2 . 8 v 2 1 0 k g n d g n d 2 1 0 k g n d 2 1 0 k 2 1 0 k g n d 2 . 8 v a g c a g c o f f a e q b e q p b e q c t l r e c e q c t l d e c k a / b s p e e d s h i f t r e g i s t e r s l a t c h e s r e c p b r e c p b application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 17 CXA1998BQ 1. system control mode playback and recording equalizer (1) playback equalizer (120 s/70 s) deck-ab (serial data d10 (pin 25)) a-eq (pin 2) b-eq (pin 3) l h l m/h l h 120 s (deck a) 70 s (deck a) according to a-eq control 120 s (deck b) 70 s (deck b) according to b-eq control (3) recording equalizer (normal, cro 2 , metal) b-eq (pin 3) rec mode l normal (type i ) m cro 2 (type ii ) h metal (type iv ) (4) recording mute (pin 14) on/off control is performed by 11-bit serial data interface d11 (pin 26). a fader function is achieved using a time constant circuit formed with the external capacitor and incorporated 20k resistor. (5) fp cal (pin 48) the standard resistor setting is 27k , but when resistance value is larger, fo (hz) is lower, and when resistance value is smaller, fo (hz) is higher. (fo: high-band peak frequency) (6) gp cal (pin 1) the standard resistor setting is 27k , but when resistance value is larger, high-band peak gain is larger, and when resistance value is smaller, high-band peak gain is smaller. (2) playback mute (pin 13) on/off control is performed by 11-bit serial data interface d7 (pin 26). a capacitor for setting the switching time constant is connected. time constant = 20k c
? 18 CXA1998BQ 2. 11-bit serial data interface d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 m2 m1 pl2 pl1 bpb bpa pb mute agc off speed deck ab rec mute pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 pin 15 low low low low low low low mute off agc function stops low, normal speed deck a selected low mute off high (open) high (open) high (open) high (open) high (open) high (open) high mute on agc function operates high (open) 1.7 deck b selected high (open) mute on output pin input set at low input set at high output data (pin 26) control signal d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 c l k ( p i n 2 5 ) d a t a ( p i n 2 6 ) l a t c h ( p i n 2 4 ) x r e s e t ( p i n 2 7 ) d 1 1 the data signal is taken in at the rising edge of the clk signal. the data signal is taken into the internal shift register when the latch signal is low. (outputs (pins 15 to 22) hold the previous value while the latch signal is low.) the internal shift register data is latched and output in parallel at the rising edge of the latch signal. (internal shift register data is loaded while the latch signal is high.) the clk signal of the 11th bit should fall after the latch signal rises. reset is done when the xreset pin is low. (asynchronous method) outputs (pins 15 to 22) are all high (open) during reset.
? 19 CXA1998BQ make sure that v dd is 4.0v or more and xreset is 1.5v or less, and 1 s or more when resetting by applying cr time constant to xreset (pin 27) and turning power on. 1 s o r m o r e 1 . 5 v o r l e s s 4 . 0 v o r m o r e v d d ( p i n 2 3 ) x r e s e t ( p i n 2 7 ) a 1 s o r m o r e 5 . 0 v 4 . 0 v o r m o r e v d d ( p i n 2 3 ) x r e s e t ( p i n 2 7 ) 0 v xreset (pin 27) input level detection is done by comparison with v dd /2. the level should be v dd /2 > xreset during the interval a. for resetting with cpu when power is turned on examples of agc control during timer recording (1) resets when power is turned on (agc function operates). (2) agc is turned off after agc inputs (pins 5 and 32) rise. (external capacitor charge of agc tc is discharged.) (3) agc is turned on and timer recording begins.
? 20 CXA1998BQ d 1 1 h l d 1 0 h l d 9 h l d 8 h l d 1 2 h l d 1 3 h l d 1 4 h l d 1 5 h l 6 x q 2 q 2 x p r 2 c l k 2 d 2 x r 2 v d d v s s x q 1 q 1 x p r 1 c l k 1 d 1 x r 1 7 4 h c 7 4 ( 1 ) x q 2 q 2 x p r 2 c l k 2 d 2 x r 2 v d d v s s x q 1 q 1 x p r 1 c l k 1 d 1 x r 1 7 4 h c 7 4 ( 2 ) x q 2 q 2 x p r 2 c l k 2 d 2 x r 2 v d d v s s x q 1 q 1 x p r 1 c l k 1 d 1 x r 1 7 4 h c 7 4 ( 3 ) x q 2 q 2 x p r 2 c l k 2 d 2 x r 2 v d d v s s x q 1 q 1 x p r 1 c l k 1 d 1 x r 1 7 4 h c 7 4 ( 4 ) y 3 a 3 b 3 y 4 a 4 b 4 v d d v s s y 2 b 2 a 2 y 1 b 1 a 1 7 4 h c 0 0 y 3 a 3 b 3 y 4 a 4 b 4 v d d v s s y 2 b 2 a 2 y 1 b 1 a 1 7 4 h c 0 8 ( 2 ) y 3 a 3 b 3 y 4 a 4 b 4 v d d v s s y 2 b 2 a 2 y 1 b 1 a 1 7 4 h c 0 8 ( 1 ) y 4 a 4 y 5 a 5 y 6 a 6 v d d v s s y 3 a 3 y 2 a 2 y 1 a 1 7 4 h c 0 4 r 5 1 0 k o n o f f s t a r t 3 o n o f f r e s e t c 5 0 . 1 4 c 1 2 0 . 1 c 9 0 . 1 c 8 0 . 1 r 3 1 0 k r 6 1 0 k c 4 0 . 1 1 8 c 1 4 0 . 1 c 1 3 0 . 1 c 2 0 0 . 1 5 1 3 1 0 0 r 1 6 1 2 7 1 4 q 1 c l o c k r e s e t q 9 q 8 q 1 0 q 1 1 v d d v s s q 2 q 3 q 4 q 7 q 5 q 6 q 1 2 7 4 h c 4 0 4 0 x a 2 b 2 x r e s 2 x q 2 q 1 c 1 r / c 1 v d d v s s r / c 2 c 2 q 2 x q 1 x r e s 1 b 1 x a 1 7 4 h c 1 2 3 b 0 a 0 b 1 a 1 a 2 b 2 a 3 v d d v s s a < b o u t a = b o u t a > b o u t a > b i n a = b i n a < b i n b 3 7 4 h c 8 5 x l o a d e n a 1 r e s e t q 9 q 8 q 1 0 q 1 1 v d d v s s e n a p d d d c d b d a c l o c k x r e s e t 7 4 h c 1 6 1 q h s e r i a l i n a b c d c l k 2 v d d v s s x q h h g f e c l k 1 s / x l 7 4 h c 1 6 5 ( 1 ) c 1 9 0 . 1 c 1 8 0 . 1 1 2 4 8 h l h l h l h l d 4 h l d 5 h l d 6 h l d 7 h l q h s e r i a l i n a b c d c l k 2 v d d v s s x q h h g f e c l k 1 s / x l 7 4 h c 1 6 5 ( 2 ) c 1 7 0 . 1 c 1 1 0 . 1 c 1 0 0 . 1 d 3 h l d 2 h l d 1 h l 8 1 7 6 8 k r 1 7 1 1 c 1 6 4 . 7 c 1 5 1 0 0 0 p r 1 3 2 . 2 k 1 r 7 2 2 0 r 8 2 2 0 r 1 5 2 2 0 r 1 4 2 2 0 r 1 1 1 0 k r 1 2 1 0 k 9 1 6 r 1 1 m r 2 2 2 0 c 6 1 5 p c 7 1 5 p 4 . 4 m h z r 4 2 2 0 r 9 2 2 0 2 l a t c h c l k d a t a x r e s e t d g n d 5 v s w g n d g n d 1 0 0 / 2 5 v c 2 1 1 5 1 0 1 9 1 0 0 r 1 8 d g n d e x c l k c 3 0 . 1 c 2 0 . 1 c 0 . 1 e x c l k 2 5 0 k h z 5 0 0 k h z 1 0 0 r 1 9 1 0 0 r 1 0 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 1 5 1 6 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 1 5 1 6 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 1 5 1 6 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 1 5 1 6 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 1 5 1 6 8 9 1 0 1 1 1 2 1 3 1 4 2 3 4 5 6 7 1 1 5 1 6 circuit diagram for 11-bit serial data transfer evaluation tool
? 21 CXA1998BQ timing chart for 11-bit serial data transfer evaluation tool d u m m y d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 2 s c o u n t r e s e t c l o c k s t o p ( 1 4 ) r e s e t / c l o c k s t o p a n d c o u n t r e s e t ( 1 5 ) d a t a h c 1 6 5 ( 1 6 ) c l k ( 1 7 ) = ( 8 ) ( 1 8 ) ( 1 9 ) l a t c h ( 1 3 ) ( 1 2 ) ( 1 1 ) h c 1 2 3 ( 1 0 ) h w h e n a = b ( 9 ) ( 8 ) c l k g a t e c o n t . ( 7 ) s / l ( 6 ) = ( 4 ) ( 5 ) ( 4 ) ( 3 ) s t a r t p u l s e ( 2 ) c l k ( 1 ) c l k the numbers (1) to (19) correspond to those of test pins for the 11-bit serial data transfer evaluation tool circuit.
? 22 CXA1998BQ detection status ams out (pin 12) signal detection low no signal detection high p b o u t 1 p b o u t 2 2 0 k 2 0 k s a l p f d e t 2 5 k h z 1 0 0 k g n d v c c v c c v c c g n d a m s g n d a m s o u t a m s t c c 1 r 1 r 2 c 2 r 3 h p f a m s g a i n i n s i d e i c 9 1 1 1 2 1 0 f c g 1 0 1 k h z 2 5 k h z 1 0 0 k h z g a i n ( d b ) f ( h z ) 3. ams (1) ams output logic ams out (pin 12) is an open collector output pin. when a 3.9 k resistor is connected to v cc = 8v: low: approximately 0.5v (i ol = 2ma (max.)) high: 8v fig. 1 shows the ams block diagram. fig. 1. ams block diagram fig. 2 shows the frequency response of the signal output from hpf. fig. 2. frequency response
? 23 CXA1998BQ (2) ams level setting the ams level is set by adjusting hpf gain and cut-off frequency with the external resistor and capacitor at pin 9. g and fc in fig. 2 are obtained from the following formula. g = 20log (1 + 100k/r1) [db] (1) fc = 1 / (2 ? ?c1 ?r1) [hz] full-wave rectifier is applied for the signal at det. signal detection time is set by the time constant of pin 11 external resistor and capacitor. det signal detection level: = ?.5dbm (typ.) = playback equalizer reference output level + ams level + hpf gain (2) playback equalizer reference output level of ?1dbm is 0db. ex.) to set ams level at ?5db, determine and set the constant for pin 9 external resistor. (calculate assuming pbout1 = pbout2) first, get the required hpf gain from formula (2). ?.5dbm = ?1dbm + (?5db) + hpfgain, so hpf gain = 38.5db. next, get pin 9 external resistance from formula (1). 38.5db = 20log (1 + 100k / r1), so r1 1.2k , and external resistance is 1.2k .
? 24 CXA1998BQ example of representative characteristics q u i e s c e n t c u r r e n t c o n s u m p t i o n v s . s u p p l y v o l t a g e v c c s u p p l y v o l t a g e [ v ] q u i e s c e n t c u r r e n t c o n s u m p t i o n [ m a ] 6 1 5 1 1 7 8 9 1 0 2 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 i c c i s t h e s u m o f t h e v c c a n d v d d c u r r e n t s . v d d = 5 . 0 v p b i n p b f b 1 p b f b 2 p b o u t p l a y b a c k e q u a l i z e r f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] 6 5 6 0 5 5 5 0 4 5 4 0 3 5 3 0 2 5 g a i n [ d b ] 2 0 5 0 1 0 0 2 0 0 5 0 0 1 k 2 k 5 k 1 0 k 2 0 k 5 0 k 1 2 0 s n s 1 2 0 s h s 7 0 s n s 7 0 s h s m v c c = 8 v 0 . 0 1 8 4 7 0 1 0 f 4 7 1 0 0 2 . 2
? 25 CXA1998BQ r e c o r d i n g e q u a l i z e r f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] o u t p u t r e s p o n s e [ d b ] 2 0 0 1 0 0 5 0 2 0 0 1 k 5 0 0 2 k 1 0 k 5 k 2 0 k 5 0 k 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 r e c o r d i n g e q u a l i z e r f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] o u t p u t r e s p o n s e [ d b ] 2 0 1 0 0 5 0 2 0 0 1 k 5 0 0 2 k 1 0 k 5 k 2 0 k 5 0 k v c c = 8 v 0 d b = n o r m n s , 3 1 5 h z , 3 0 d b m 2 4 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 4 v c c = 8 v 0 d b = n o r m n s , 3 1 5 h z , 3 0 d b m ( t a p e ) ( s p e e d ) n o r m h s c r o 2 h s m e t a l h s ( t a p e ) ( s p e e d ) n o r m h s c r o 2 h s m e t a l h s
? 26 CXA1998BQ a m s q u i e s c e n t d e t e c t i o n l e v e l f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] 3 0 2 5 2 0 1 5 1 0 5 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 a m s i n p u t l e v e l ( p l a y b a c k e q u a l i z e r o u t p u t l e v e l ) [ d b ] 2 0 5 0 1 0 0 2 0 0 5 0 0 1 k 2 k 5 k 1 0 k 2 0 k 5 0 k v c c = 8 v 1 2 0 s n s a m s o u t 8 v 0 d b = 2 1 d b m , 3 1 5 h z ( p l a y b a c k e q u a l i z e r r e f e r e n c e o u t p u t l e v e l ) a b a : p i n 9 r 9 . 1 k c 0 . 0 1 5 b : p i n 9 r 1 k c 0 . 1 a m s g a i n a m s t c a m s o u t 0 . 1 1 0 0 k 1 0 0 k t o 8 v a : 0 . 0 1 5 9 . 1 k b : 0 . 1 1 k 9 1 1 1 2 a g c o u t p u t c h a r a c t e r i s t i c s a g c t c 4 7 3 0 0 k v c c = 8 v 1 k h z a g c o f f a g c o n 1 0 5 0 5 1 0 1 5 3 5 3 0 2 5 2 0 1 5 1 0 5 i n p u t l e v e l [ d b m ] o u t p u t l e v e l [ d b m ] 4
? 27 CXA1998BQ r e c o r d i n g e q u a l i z e r t o t a l h a r m o n i c d i s t o r t i o n o u t p u t l e v e l [ d b m ] t . h . d + n o i s e [ % ] 1 5 1 0 0 5 0 . 1 0 . 2 0 . 5 1 . 0 2 . 0 v c c = 8 v n o r m n s r l = 2 . 7 k w 1 k h z 0 d b = 1 0 d b m 1 0 5 p l a y b a c k e q u a l i z e r t o t a l h a r m o n i c d i s t o r t i o n o u t p u t l e v e l [ d b m ] t . h . d + n o i s e [ % ] 3 0 5 1 5 1 0 0 . 1 0 . 2 0 . 5 1 . 0 2 . 0 v c c = 8 v 1 2 0 s n s r l = 2 . 7 k w 1 k h z 2 5 2 0
? 28 CXA1998BQ package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e m p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r / p a l l a d i u m p l a t i n g c o p p e r / 4 2 a l l o y 4 8 p i n q f p ( p l a s t i c ) 1 5 . 3 0 . 4 1 2 . 0 0 . 1 + 0 . 4 0 . 8 0 . 3 0 . 1 + 0 . 1 5 0 . 1 2 1 3 2 4 2 5 3 6 3 7 4 8 1 1 2 2 . 2 0 . 1 5 + 0 . 3 5 0 . 9 0 . 2 0 . 1 0 . 1 + 0 . 2 1 3 . 5 0 . 1 5 0 . 1 5 0 . 0 5 + 0 . 1 q f p - 4 8 p - l 0 4 * q f p 0 4 8 - p - 1 2 1 2 - b 0 . 7 g n o t e : p a l l a d i u m p l a t i n g t h i s p r o d u c t u s e s s - p d p p f ( s o n y s p e c . - p a l l a d i u m p r e - p l a t e d l e a d f r a m e ) .

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